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V
CY7C43644AV PRELIMINARY CY7C43664AV/CY7C43684AV
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching
Features
* 3.3V high-speed, low-power, bidirectional, First-In FirstOut (FIFO) memories w/ bus matching capabilities * 1Kx36x2 (CY7C43644AV) * 4Kx36x2 (CY7C43664AV) * 16Kx36x2 (CY7C43684AV) * 0.25-micron CMOS for optimum speed/power * High-speed 133-MHz operation (7.5-ns read/write cycle times) * Low power -- ICC= 60 mA -- ISB= 12 mA * Fully asynchronous and simultaneous read and write operation permitted * Mailbox bypass register for each FIFO * Parallel and Serial Programmable Almost Full and Almost Empty flags * Retransmit function * Standard or FWFT mode user selectable * Partial Reset * Big or Little Endian format for word or byte bus sizes * 128-Pin TQFP packaging * 3.3V pin-compatible, feature enhanced, density upgrade to IDT723624/34/44 family * Easily expandable in width and depth
Logic Block Diagram
MBF1 CLKA CSA W/RA ENA MBA RT2
Input Register
Register
MRS1 PRS1
FIFO1, Mail1 Reset Logic
Write Pointer
Read Pointer
FFA/IRA AFA
Status Flag Logic
Output
1K/4K/16K x36 Dual Ported Memory
Bus Matching
Port A Control Logic
Mail1 Register
CLKB CSB W/RB ENB MBB RTI BE BM SIZE
Port B Control Logic
EFB/ORB AEB
SPM FS0/SD FS1/SEN A0-35 EFA/ORA AEA
36
Programmable Flag Offset Registers
Timing Mode
36
B0-35 BE/FWFT
Status Flag Logic Write Pointer Read Pointer
FFB/IRB AFB
Output Register
1K/4K/16K x36 Dual Ported Memory
Mail2 Register
MBF2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
Input Register
FIFO1, Mail1 Reset Logic
MRS2 PRS2
*
CA 95134
*
408-943-2600 August 30, 1999
PRELIMINARY
Pin Configuration
TQFP Top View
CSA FFA/IRA EFA/ORA PRS1
CY7C43644AV CY7C43664AV/CY7C43684AV
W/RA ENA CLKA GND A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/FWFT GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 RT2 A12 GND A11 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
EFB/ORB FFB/IRB GND CSB W/RB ENB
VCC AFA AEA MBF2 MBA MRS1 FS0/SD GND GND FS1/SEN MRS2 MBB
MBF1 VCC AEB AFB
CLKB PRS2 VCC B35 B34 B33 B32 GND GND B31 B30 B29 B28 B27 B26 RT1 B25 B24 BM GND B23 B22 B21 B20 B19 B18 GND B17 B16 SIZE VCC B15 B14 B13 B12 GND B11 B10
CY7C43644AV CY7C43664AV CY7C43684AV
GND A5 A4 A3 SPM VCC A2 A1 A0 GND B0 B1
2
GND B6 VCC B7 B8 B9
A9 A8 A7 A6
B2 B3 B4 B5
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PRELIMINARY
Functional Description
The CY7C436X4AV is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 133 MHz and has read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or Little Endian configurations. The CY7C436X4AV is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on the CY7C436X4AV: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. Each FIFO has its own independent Master Reset pin, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. The CY7C436X4AV have two modes of operation: In the CY Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through mode (FWFT), the first
CY7C43644AV CY7C43664AV/CY7C43684AV
long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready flag (EFA/ ORA and EFB/ORB) and a combined Full/Input Ready flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the CY Standard mode. EF indicates whether the memory is full or not. The IR and OR functions are selected in the FirstWord Fall-Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost Empty flag (AEA and AEB) and a programmable Almost Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined "almost empty state." AFA and AFB indicate when a selected number of words written to the memory achieve a predetermined "almost full state." IRA, IRB, AFA, and AFB are synchronized to the port clock that writes data into its array. ORA, ORB, AEA, and AEB are synchronized to the port clock that reads data from its array. Programmable offset for AEA, AEB, AFA, and AFB are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16, or 64 locations from the empty boundary and AFA and AFB threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more devices may be used in parallel to create wider data paths. If at any time the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. A Retransmit feature is available on these devices. The CY7C436X4AV are characterized for operation from 0C to 70C. Input ESD protection is greater than 2001V, and latchup is prevented by the use of guard rings.
Selection Guide
CY7C43644/64/84AV -7 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1 ) (mA) Commercial Industrial CY7C43644AV Density Package 1K x 36 x2 128 TQFP CY7C43664AV 4K x 36 x2 128 TQFP 133 6 7.5 3 0 6 60 CY7C43644/64/84AV -10 100 8 10 4 0 8 60 CY7C43644/64/84AV -15 66.7 10 15 5 0 10 60 60 CY7C43684AV 16K x 36 x2 128 TQFP
3
PRELIMINARY
Pin Definitions
Signal Name A0-35 AEA Description Port A Data Port A Almost Empty Flag Port B Almost Empty Flag Port A Almost Full Flag Port B Almost Full Flag Port B Data Big Endian/ First-Word FallThrough Select I/O I/O O
CY7C43644AV CY7C43664AV/CY7C43684AV
Function 36-bit bidirectional data port for side A. Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register, X2. Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register, X1. Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset register, Y1. Programmable Almost Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset register, Y2. 36-bit bidirectional data port for side B. This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on Port A. The A0-35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on Port B. The B0-35 outputs are in the high-impedance state when CSB is HIGH. This is a dual-function pin. In the CY Standard mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0-35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual-function pin. In the CY Standard mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B0-35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
AEB
O
AFA
O
AFB
O
B0-35 BE/FWFT
I/O I
BM
Bus Match Select (Port A)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA CSB EFA/ORA
Port A Chip Select Port B Chip Select Port A Empty/ Output Ready Flag Port B Empty/ Output Ready Flag Port A Enable Port B Enable Port A Full/Input Ready Flag
I I O
EFB/ORB
O
ENA ENB FFA/IRA
I I O
4
PRELIMINARY
Pin Definitions (continued)
Signal Name FFB/IRB Description Port B Full/Input Ready Flag I/O O
CY7C43644AV CY7C43664AV/CY7C43684AV
Function This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register programming, FS1/ SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 40 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-35 outputs are active, a HIGH level on MBA selects data from the Mail2 register for output and a LOW level selects FIFO2 output register data for output. A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-35 outputs are active, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO1 output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW. A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. A LOW strobe on this pin will retransmit data on FIFO1 from the location of the write pointer at the last Partial or Master reset. A LOW strobe on this pin will retransmit data on FIFO2 from the location of the write pointer at the last Partial or Master reset. A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
FS1/SEN
Flag Offset Select 1/Serial Enable Flag Offset Select 0/Serial Data
I
FS0/SD
I
MBA
Port A Mailbox Select Port B Mailbox Select Mail1 Register Flag
I
MBB
I
MBF1
O
MBF2
Mail2 Register Flag
O
MRS1
FIFO1 Master Reset
I
MRS2
FIFO2 Master Reset
I
PRS1
FIFO1 Partial Reset
I
PRS2
FIFO2 Partial Reset
I
RT1 RT2 SIZE
Retransmit FIFO1 Retransmit FIFO2 Bus Size Select
I I I
5
PRELIMINARY
Pin Definitions (continued)
Signal Name SPM W/RA Description Serial Programming Port A Write/ Read Select Port B Write/ Read Select I/O I I
CY7C43644AV CY7C43664AV/CY7C43684AV
Function A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming or default offsets (8, 16, or 64). A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0-35 outputs are in the high-impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0-35 outputs are in the high-impedance state when W/RB is LOW. Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
W/RB
I
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................... -65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2]...................................-0.5V to VCC+0.5V Output Current into Outputs (LOW) ............................. 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC[3] 3.3V 10% 3.3V 10%
Electrical Characteristics Over the Operating Range
CY7C43644/64/84AV Parameter VOH VOL VIH VIL IIX IOZL IOZH ICC1[4] ISB[5] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC = Max. VSS < VO< VCC Com'l Ind Com'l Ind Test Conditions VCC = 3.0V, IOH = -2.0 mA VCC = 3.0V, IOL = 8.0 mA 2.0 -0.5 -10 -10 Min. 2.4 0.5 VCC 0.8 +10 +10 60 60 12 12 Max. Unit V V V V A A mA mA mA mA
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 4 8 Unit pF pF
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3. Operating VCC Range for -7 speed is 3.3V 5%. 4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are unloaded. 5. All inputs = VCC - 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded. 6. Tested initially and after any design or process changes that may affect these parameters.
6
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
R1=330 3.3V OUTPUT CL=30 pF INCLUDING JIG AND SCOPE R2=680 3.0V GND 3 ns
CY7C43644AV CY7C43664AV/CY7C43684AV
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
AC Test Loads and Waveforms (-7)
V CC/2 50 I/O
Z0=50 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
Switching Characteristics Over the Operating Range
CY7C43644/ 64/84AV -7 Parameter fS tCLK tCLKH tCLKL tDS tENS tRSTS tFSS tBES tSPMS tSDS tSENS tFWS tDH tENH Description Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA or CLKB LOW Set-Up Time, A0-35 before CLKA and B0-35 before CLKB Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA or CLKB[7] Set-Up Time, FS0 and FS1 before MRS1 and MRS2 HIGH Set-Up Time, BE/FWFT before MRS1 and MRS2 HIGH Set-Up Time, SPM before MRS1 and MRS2 HIGH Set-Up Time, FS0/SD before CLKA Set-Up Time, FS1/SEN before CLKA Set-Up Time, BE/FWFT before CLKA Hold Time, A 0-35 after CLKA and B 0-35 after CLKB Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB 7.5 3.5 3.5 3 3 2.5 5 5 5 3 3 0 0 1 Min. Max. 133 10 4 4 4 4 4 7 7 7 4 4 0 0 2 CY7C43644/ 64/84AV -10 Min. Max. 100 15 6 6 5 5 5 7.5 7.5 7.5 5 5 0 0 0 CY7C43644/ 64/84AV -15 Min. Max. 67 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
7
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
CY7C43644/ 64/84AV -7 Parameter tRSTH tFSH tBEH tSPMH tSDH tSENH tSPH tSKEW1[8] tSKEW2[8] tA tWFF tREF tPAE tPAF tPMF Description Hold Time, MRS1, MRS2, PRS1, or PRS2 LOW after CLKA or CLKB[7] Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH Hold Time, SPM after MRS1 and MRS2 HIGH Hold Time, FS0/SD after CLKA Hold Time, FS1/SEN after CLKA Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH Skew Time between CLKA and CLKB for EFA/ ORA, EFB/ORB, FFA/IRA, and FFB/IRB Skew Time between CLKA and CLKB for AEA, AEB, AFA, AFB Access Time, CLKA to A0-35 and CLKB to B0-35 Propagation Delay Time, CLKA to FFA/IRA and CLKB to FFB/IRB Propagation Delay Time, CLKA to EFA/ORA and CLKB to EFB/ORB Propagation Delay Time, CLKA to AEA and CLKB to AEB Propagation Delay Time, CLKA to AFA and CLKB to AFB Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-35[9] and CLKB to A0-35[10] Propagation Delay Time, MBA to A0-35 Valid and MBB to B0-35 Valid Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, FFA / IRA LOW, EFB /ORB LOW and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, FFB / IRB LOW, EFA /ORA LOW and MBF2 HIGH Enable Time, CSA or W/RA LOW to A0-35 Active and CSB LOW and W/RB HIGH to B0-35 Active Disable Time, CSA or W/RA HIGH to A0-35 at High Impedance and CSB HIGH or W/RB LOW to B0-35 at High Impedance Retransmit pulse Width Retransmit Recovery Time Min. 1 1 0 0 0 5 2 7.5 7 1 1 1 1 1 0 6 6 6 6 6 6 Max.
CY7C43644/ 64/84AV -10 Min. 1 1 0 0 1 5 2 7.5 8 1 1 1 1 1 0 8 8 8 8 8 8 Max.
CY7C43644/ 64/84AV -15 Min. 4 2 2 2 0 0 2 7.5 12 3 2 1 1 1 0 10 10 10 10 10 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tPMR tMDV tRSF
1 1 1
7 6 6
2 2 1
11 9 10
3 3 1
12 11 15
ns ns ns
tEN tDIS
1 1
5 5
2 1
8 6
2 1
10 8
ns ns
tPRT tRTR
60 90
60 90
60 90
ns ns
Notes: 8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle. 9. Writing data to the Mail1 register when the B0-35 outputs are active and MBB is HIGH. 10. Writing data to the Mail2 register when the A0-35 outputs are active and MBA is HIGH.
8
PRELIMINARY
Switching Waveforms
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight CLKA CLKB
t RSTS
CY7C43644AV CY7C43664AV/CY7C43684AV
[11, 12]
tRSTS t FWS
MRS1
tBES tBEH
BE/FWFT
tSPMS
BE
tSPMH
FWFT
SPM
tFSS tFSH
FS1/SEN, FS0/SD FFA/IRA
tRSF
tWFF
tRSF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
Notes: 11. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value. 12. PRS1 must be HIGH during Master Reset.
9
PRELIMINARY
Switching Waveforms (continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes) CLKA CLKB
[13, 14]
CY7C43644AV CY7C43664AV/CY7C43684AV
tRSTH tRSTS
PRS1
tRSF tWFF
FFA/IRA
tRSF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (CY Standard and FWFT Modes) [15] CLKA MRS1, MRS2
tFSS tFSH
SPM
tFSS tFSH
FS1/SEN, FS0/SD FFA/IRA
tWFF tENS tENH tSKEW1 [16]
ENA
tDS tDH
A0 - 35
AFA Offset (Y1) AEB Offset (X1) AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1
CLKB FFB/IRB
Notes: 13. Partial Reset is performed in the same manner for FIFO2. 14. MRS1 must be HIGH during Partial Reset. 15. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. 16. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
10
PRELIMINARY
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes) CLKA MRS1, MRS2
tFSS tFSH
CY7C43644AV CY7C43664AV/CY7C43684AV
[17]
SPM
tWFF tSKEW1 tFSS tSPH tSENS tSENH tSENS tSENH
FFA/IRA FS1/SEN
tSDS tSDH tSDS
tSDH
FS0/SD [18]
AFA Offset (Y1) MSB AEA Offset (X2) LSB
CLKB
tWFF
FFA/IRA
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t CLK tCLKH tCLKL
CLKA FFA/IRA
HIGH
CSA
tENS
tENH
tENS tENH
W/RA
tENS tENH
MBA
tENS tENH tENS tENH t ENS t ENH
ENA
tDS tDH W2[19]
A0-35
W1[19]
Notes: 17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH. 18. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2). 19. Written to FIFO1.
11
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tCLK tCLKH t CLKL
CLKB FFB/IRB CSB
tENS tENH
HIGH tENS tENH
W/RB
tENS tENH
MBB
tENS tENH tENS tENH tENS tENH
ENB
tDS tDH
[20]
B0-35
W1
W2[20]
Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes) CLKB FFB/IRB CSB
t ENS
HIGH tENS tENH
W/RB
tENS tENH tENS tENH
MBB
tENS tENH tENS tENH
ENB
tDS tDH
B0-17
Note: 20. Written to FIFO2.
12
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Port B Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB FFB/IRB CSB
tENS
HIGH tENS tENH
W/RB
tENS tENH tENH
MBB
tENS tENH tENS tENH
ENB
tDS tDH
B0-8
Port B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLK tCLKH tCLKL
CLKB EFB/ORB CSB W/RB MBB
tENS tENH tENS tENH t ENS tEN
ENB B0-35
(Standard Mode) OR
t EN tMDV tA Previous Data tEN t MDV tA W1[21] W1
[21]
tA
No Operation W2
[21]
tDIS
tA
tDIS
B0-35
(FWFT Mode)
] W2 [21
] W3[21
Note: 21. Read From FIFO1.
13
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes) CLKB
[22]
EFB/ORB CSB W/RB MBB
HIGH
tENS tENH
ENB B0-8
(Standard Mode) OR
tEN tMDV tA Previous Data tEN tMDV tA Read 1 tA Read 1 tA Read 2 Read 3 tA Read 2 tA tA Read 3 tA Read 4 No OperationtDIS Read 4 tDIS Read 5
B0-8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[23] CLKB EFB/ORB CSB W/RB MBB
tENS tENH
ENB B0-17
(Standard Mode) OR
tEN tMDV tA Previous Data tEN tMDV tA Read 1 Read 2 Read 1 tA Read 3 tA No Operation Read 2 tDIS tDIS
B0-17
(FWFT Mode)
Notes: 22. Unused word B18-35 contains all zeroes for word-size reads. 23. Unused bytes B9-17, B18-26 , and B27-35 contain all zeroes for byte-size reads.
14
PRELIMINARY
Switching Waveforms (continued)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tCLK t CLKH tCLKL
CY7C43644AV CY7C43664AV/CY7C43684AV
CLKA EFA/ORA CSA W/RA MBA
tENS tENH tENS tENH tENS tENH
ENA A0-35
(Standard Mode) OR
tEN tMDV tA Previous Data tEN tMDV W1[24] tA W2
[24]
tA W1 [24] tA
No Operation W2
[24]
tDIS
tDIS W3[24]
A0-35
(FWFT Mode)
Note: 24. Read From FIFO2.
15
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)[25]
tCLK tCLKH tCLKL
CLKA
CSA W/RA MBA
LOW HIGH tENS tEN
t ENS tEN
ENA FFA/IRA A0-35 CLKB
HIGH t DS tDH W1 tSKEW[26] tCLKH tCLKL
tCLK
tREF
tREF
EFB/ORB CSB W/RB
FIFO1 Empty
LOW
HIGH
MBB ENB
LOW tENS tENH
tA
B0-35
Old Data in FIFO1 Output Register
W1
Notes: 25. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively. 26. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1 , then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown.
16
PRELIMINARY
Switching Waveforms (continued)
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY Standard Mode) CLKA
[25]
tCLK tCLKH t CLKL
CY7C43644AV CY7C43664AV/CY7C43684AV
CSA W/RA MBA
LOW HIGH tENS tENH
tENS tENH
ENA FFA/IRA A0-35 CLKB
tCLK tREF tREF
HIGH tDS tDH W1 tSKEW[27] tCLKH tCLKL
EFB/ORB CSB W/RB MBB ENB
FIFO1 Empty
LOW
HIGH
LOW t ENS tENH
tA
B0-35
W1
Note: 27. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1 , then the transition of EFB HIGH may occur one CLKB cycle later than shown.
17
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
[28]
tCLK tCLKH tCLKL
CLKB
CSB W/RB MBB
LOW
LOW tENS tENH
tENSt ENH
ENB FFB/IRB B0-35 CLKA
tCLK tREF tREF HIGH tDS tDH W1
] tSKEW1[29
tCLKH
tCLKL
EFA/ORA CSA W/RA MBA ENA
FIFO2 Empty
LOW
LOW
LOW tENStENH
tA
A0-35
Old Data in FIFO2 Output Register
W1
Notes: 28. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 29. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1 , then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown.
18
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode) [28]
tCLK t CLKH tCLKL
CLKB
CSB W/RB MBB
LOW
LOW tENS tENH
tENS tENH
ENB FFB/IRB B0-35 CLKA
tCLK tREF t REF HIGH tDS tDH W1 tSKEW1[30] tCLKH tCLKL
EFA/ORA CSA W/RA MBA ENA
FIFO2 Empty
LOW
LOW
LOW tENStENH
tA
A0-35
W1
Note: 30. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
19
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) [28]
tCLK tCLKH tCLKL
CLKB
CSB W/RB MBB
LOW
HIGH
tENS tENH
ENB EFB/ORB B0-35 CLKA
tCLK tWFF tWFF HIGH tA
Previous Word in FIFO1 Output Register Next Word From FIFO1
tSKEW1
[31]
tCLKH
tCLKL
FFA/IRA CSA W/RA MBA
FIFO1 Full
LOW
HIGH t ENS tENH
tENS tENH
ENA
tDS tDH
A0-35
To FIFO1
Note: 31. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
20
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode) [28]
tCLK tCLKH tCLKL
CLKB
CSB W/RB MBB
LOW
HIGH
tENS tENH
ENB EFB/ORB B0-35 CLKA
tCLK tWFF t WFF HIGH tA
Previous Word in FIFO1 Output Register Next Word From FIFO1
tSKEW1[32]
tCLKH
tCLKL
FFA/IRA CSA W/RA MBA
FIFO1 Full
LOW
HIGH tENS tENH
t ENS tENH
ENA
tDS tDH
A0-35
Note: 32. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
21
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
tCLK t CLKH tCLKL
[33]
CLKA
CSA W/RA MBA ENA EFA/ORA A0-35 CLKB
LOW
LOW
LOW tENS tENH
HIGH tA
Previous Word in FIFO2 Output Register Next Word From FIFO2
tSKEW1[34]
tCLKH
tCLKL
tCLK
tWFF
tWFF
FFB/IRB CSB W/RB MBB
FIFO2 Full
LOW
LOW tENS tENH
tENS tENH
ENB
tDS tDH
B0-35
To FIFO2
Notes: 33. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long-word, respectively. 34. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
22
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
t CLK tCLKH tCLKL
[35]
CLKA
CSA W/RA MBA ENA EFA/ORA A0-35 CLKB
LOW
LOW
LOW tENSt ENH
HIGH tA
Previous Word in FIFO12 Output Register Next Word From FIFO2
tSKEW1 [36]
tCLKH
tCLKL
tCLK
tWFF
tWFF
FFB/IRB CSB W/RB MBB
FIFO2 Full
LOW
LOW tENS tENH
tENS tENH
ENB
tDS tDH
B0-35
To FIFO2
Notes: 35. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long-word, respectively. 36. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
23
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[37, 38]
CLKA
tENS tENH
ENA
tSKEW2[39]
CLKB
tPAE tPAE (X1+1)Words in FIFO1 t ENS tENH
AEB ENB
X1 Word in FIFO1
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [40, 41]
CLKB
tENS tENH
ENB
tSKEW2 [42]
CLKA
tPAE tPAE (X2+1)Words in FIFO2 tENS
AEA ENA
X2 Word in FIFO2
tENH
Notes: 37. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 38. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively. 39. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2 , then AEB may transition HIGH one CLKB cycle later than shown. 40. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 41. If Port B size is word or byte, t SKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively. 42. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2 , then AEA may transition HIGH one CLKA cycle later than shown.
24
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
[41, 43, 44]
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
tSKEW2[45]
CLKA
tENS tENH
ENA
tPAF
AFA
t PAF (D-Y1)Words in FIFO1
[D-(Y1+1)] Words in FIFO1
CLKB
tENS
tENH
ENB
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)
tSKEW2 [47]
[40, 44, 46]
CLKB
tENS tENH
ENB
tPAF
AFB
tPAF (D-Y2)Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS tENH
ENA
Notes: 43. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 44. D = Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV. 45. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown. 46. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long-word, respectively. 47. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2 , then AFB may transition HIGH one CLKA cycle later than shown.
25
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) CLKA
t ENS tENH
[48]
CSA
tENS t ENH
W/RA
tENS tENH
MBA
tENS t ENH
ENA
tDS tDH W1
A0-35 CLKB
tPMF
tPMF
MBF1 CSB W/RB MBB
tENS tENH
ENB
t EN tMDV FIFO1 Output Register tPMR tDIS W1 (Remains valid in Mail1 Register after read)
Note: 48. If Port B is configured for word size, data can be written to the Mail1 register using A0-17 (A18-35 are "Don't Care" inputs). In this first case B0-17 will have valid data (B18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-8 (A9-35 are "Don't Care" inputs). In this second case, B0-8 will have valid data (B9-35 will be indeterminate).
26
PRELIMINARY
Switching Waveforms (continued)
CY7C43644AV CY7C43664AV/CY7C43684AV
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [49]
CLKB
tENS tENH
CSB
tENS tENH
W/RB
t ENS tENH
MBB
tENS tENH
ENB
tDS t DH
B0-35 CLKA
W1
tPMF
tPMF
MBF2 CSA W/RA MBA
tENS tENH
ENA
tEN tMDV FIFO2 Output Register tPMR tDIS W1 (Remains valid in Mail2 Register after read)
A0-35
FIFO1 Retransmit Timing RT1
[50, 51, 52, 53]
tPRT
tRTR
ENB
EFB/FFA
Notes: 49. If Port B is configured for word size, data can be written to the Mail2 register using B0-17 (B18-35 are "Don't Care" inputs). In this first case A0-17 will have valid data (A18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-8 (B9-35 are "Don't Care" inputs). In this second case, A0-8 will have valid data (A9-35 will be indeterminate). 50. Retransmit is performed in the same manner for FIFO2. 51. Clocks are free running in this case. 52. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 53. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
27
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2) Each of the two FIFO memories of the CY7C436X4AV undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory. A LOW-to-HIGH transition on a FIFO Master Reset (MRS1, MRS2) input latches the value of the Big Endian (BE) input or determining the order by which bytes are transferred through Port B. A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2) input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below). Partial Reset (PRS1, PRS2) Each of the two FIFO memories of the CY7C436X4AV undergoes a limited reset by taking its associated Partial Reset (PRS1, PRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA, AFB) HIGH. A Partial Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient. Big Endian/First Word Fall Through (BE/FWFT) This is a dual-purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of Big or Little Endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long word size, the Big Endian function has no application and the BE input is a "Don't Care".) A HIGH on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Big En-
CY7C43644AV CY7C43664AV/CY7C43684AV
dian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the longword written to Port A will be read from Port B first; the least significant byte (word) of the long word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the most significant byte (word) of the long-word; the byte (word) written to Port B last will be read from Port A as the least significant byte (word) of the longword. A LOW on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long word written to Port A will be read from Port B first; the most significant byte (word) of the long-word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from port A as the least significant byte (word) of the long-word; the byte (word) written to Port B last will be read from Port A as the most significant byte (word) of the longword. After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: CY Standard mode or First-Word Fall-Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the BE/FWFT input at the second LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Standard mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In CY Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0-35 or B0-35). It also uses the Input Ready function (IRA, IRB) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Master Reset, the level applied to the BE/FWFT input to choose the desired timing mode must remain static throughout the FIFO operation. Programming the Almost Empty and Almost Full Flags Four registers in the CY7C436X4AV are used to hold the offset values for the Almost Empty and Almost Full flags. The Port B Almost Empty flag (AEB) offset register is labeled X1 and the Port A Almost Empty flag (AEA) offset register is labeled X2. The Port A Almost Full flag (AFA) offset register is labeled Y1 and the Port B Almost Full flag (AFB) offset register is labeled Y2. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO's Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). To load a FIFO's Almost Empty flag and Almost Full flag offset registers with one of the three preset values listed in Table 1, the Serial Pro-
28
PRELIMINARY
gram Mode (SPM) and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH transition of its Master Reset input (MRS1 and MRS2). For example, to load the preset value of 64 into X1 and Y1, SPM, FS0, and FS1 must be HIGH when FIFO1 reset (MRS1) returns HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with Master Reset (MRS2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times. To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the offset registers are (A0-7), (A0-8), (A 0-9), (A0-11), or (A 0-13), for the CY7C436X4AV, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 1012 for the CY7C43644AV; 1 to 4092 for the CY7C43664AV; 1 to 16380 for the CY7C43684AV. After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin normal operation. To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-toHIGH transition of CLKA that the FS1/SEN input is LOW. Thirty-two, thirty-six, forty, forty-eight, or fifty-six bit writes are needed to complete the programming for the CY7C436X4AV, respectively. The four registers are written in the order Y1, X1, Y2, and, finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 1020 (CY7C43644AV), 1 to 4092 (CY7C43664AV), or 1 to 16380 (CY7C43684AV). When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written. FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO1 operation. The Port B Full/Input ready (FFB/IRB) flag also remains LOW throughout the serial programming process, until all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition of CLKB after the last bit is loaded to allow normal FIFO2 operation. SPM, FS0/SD, and FS1/SEN function the same way in both CY Standard and FWFT modes. FIFO Write/Read Operation The state of the Port A data (A0-35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read Select (W/RA). The A0-35 lines are in the high-impedance state when either CSA or W/RA is HIGH. The A0-35 lines are active outputs when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-35 inputs on a LOW-toHIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
CY7C43644AV CY7C43664AV/CY7C43684AV
writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-35 inputs on a LOW-toHIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation. The set-up and hold time constraints to the port clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/Read select may change states during the set-up and hold time window of the cycle. When operating the FIFO in FWFT mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO's output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in CY Standard mode, regardless of whether the Empty Flag is LOW or HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/ Read select, Enable, and Mailbox select. Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Table 4 and Table 5 show the relationship of each port flag to FIFO1 and FIFO2. Empty/Output Ready Flags (EFA/ORA, EFB/ORB) These are dual-purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. In the CY Standard mode, the Empty Flag (EFA, EFB) function is selected. When the Empty Flag is HIGH, data is available in the FIFO's RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
29
PRELIMINARY
The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. In FWFT Mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. In the CY Standard mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Full/Input Ready Flags (FFA/IRA, FFB/IRB) This is a dual-purpose flag. In FWFT mode, the Input Ready (IRA and IRB) function is selected. In CY Standard mode, the Full Flag (FFA and FFB) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/ Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/ Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle.
CY7C43644AV CY7C43664AV/CY7C43684AV
Almost Empty Flags (AEA, AEB) The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. Almost Full Flags (AFA, AFB) The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The Almost Full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024-Y), (4096-Y), or (16384-Y) for the CY7C436X4AV respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024-(Y+1)], [4096-(Y+1)], or [16384-(Y+1)], for the CY7C436X4AV respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [1024/4096/16384-(Y+1)]. An Almost Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. A LOWto-HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle.
30
PRELIMINARY
Mailbox Registers Each FIFO has a 36-bit bypass register to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. A LOW-to-HIGH transition on CLKA writes A0-35 data to the Mail1 Register when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data lines A 0-35. If the selected Port A bus size is 18 bits, then the usable width of the Mail1 Register employs data lines A0-17. (In this case, A18-35 are "Don't Care" inputs.) If the selected Port A bus size is 9 bits, then the usable width of the Mail1 Register employs data lines A0-8. (In this case, A9-35 are "Don't Care" inputs.) A LOW-to-HIGH transition on CLKB writes B0-35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is also 36 bits, then the usable width of the Mail2 Register employs data lines B 0-35. If the selected Port B bus size is 18 bits, then the usable width of the Mail2 Register employs data lines B0-17. (In this case, B18-35 are don't care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail2 Register employs data lines B0-8. (In this case, B9-35 are don't care inputs.) Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B 0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-17. (In this case, B18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on B0-8. (In this case, B9-35 are indeterminate.) The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on A0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on A0-17. (In this case, A18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on A0-8. (In this case, A9-35 are indeterminate.) The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data.
CY7C43644AV CY7C43664AV/CY7C43684AV
Bus Sizing The Port B bus can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. The levels applied to the Port B Bus Size Select (SIZE) and the Bus Match Select (BM) determine the Port B bus size. These levels should be static throughout FIFO operation. Both bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH. Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte- or word-size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW-to-HIGH transition of MRS1 and MRS2 selects the endian method that will be active during FIFO operation. BE is a "Don't Care" input when the bus size selected for Port B is long word. The endian method is implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH. Only 36-bit long-word data is written to or read from the two FIFO memories on the CY7C436X4AV. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to FIFO2 RAM. These bus-matching operations are not available when transferring data via mailbox registers. Furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. In this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don't care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A0-17 and B0-17. When a byte-size bus is selected, then mailbox data can be transmitted only between A0-8 and B 0-8. Bus-Matching FIFO1 Reads Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire longword immediately shifts to the FIFO1 output register. If byte or word size is implemented on Port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long-word stored in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of the long word to the FIFO1 output register. When reading data from FIFO1 in the byte or word format, the unused B0-35 outputs are indeterminate. Bus-Matching FIFO2 Writes Data is written to the FIFO2 RAM in 36-bit long-word increments. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long-word to FIFO2 also stores the entire long word in FIFO2 RAM. When reading data from FIFO2 in byte or word format, the unused B0-35 outputs are LOW.
31
PRELIMINARY
Retransmit (RT1, RT2) The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last reset cycle. A LOW pulse on RT1, RT2 resets the internal read pointer to the first physical location of the FIFO. CLKA and CLKB
CY7C43644AV CY7C43664AV/CY7C43684AV
may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT1, RT2 are transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
32
PRELIMINARY
.
CY7C43644AV CY7C43664AV/CY7C43684AV
A27-35
A18-26
BYTE ORDER ON PORT A:
BE X BM L SIZE X
A9-17
A0-8
A
B27-35
B
B18-26
C
B9-17
D
B0-8
Write to FIFO
A
B27-35
B
B18-26
C
B9-17
D
B0-8
Read from FIFO
(a) LONG-WORD SIZE 1st: Read from FIFO 2nd: Read from FIFO
BE H
BM H
SIZE L B27-35 B18-26
A
B9-17
B
B0-8
C
B27-35 BE L BM H SIZE L B27-35 B18-26 B18-26 B9-17
D
B0-8
(b) WORD SIZE - BIG ENDIAN 1st: Read from FIFO 2nd: Read from FIFO
C
B9-17
D
B0-8
A
B27-35 BE H BM H SIZE H B27-35 B18-26 B9-17 B18-26 B9-17
B
B0-8
(c) WORD SIZE - LITTLE ENDIAN 1st: Read from FIFO 2nd: Read from FIFO 3rd: Read from FIFO 4th: Read from FIFO
A
B0-8
B
B27-35 B18-26 B9-17 B0-8
C
B27-35 B18-26 B9-17 B0-8
D
(d) BYTE SIZE - BIG ENDIAN
B27-35 BE L BM H SIZE H B27-35 B18-26 B9-17 B18-26 B9-17 B0-8
D
B0-8
1st: Read from FIFO 2nd: Read from FIFO 3rd: Read from FIFO 4th: Read from FIFO
C
B27-35 B18-26 B9-17 B0-8
B
B27-35 B18-26 B9-17 B0-8
A
(e) BYTE SIZE - LITTLE ENDIAN
33
PRELIMINARY
Table 1. Flag Programming SPM H H H H H H H L L L L
..
CY7C43644AV CY7C43664AV/CY7C43684AV
FS1/ SEN H H H H L L L H H L L
FS0/ SD H H L L H H L L H H L
MRS1 X X X
MRS2 X X X
X1 and Y1 Registers[54] 64 X 16 X 8 X Parallel programming via Port A Serial programming via SD Reserved Reserved Reserved
X2 andY2 Registers[55] X 64 X 16 X 8 Parallel programming via Port A Serial programming via SD Reserved Reserved Reserved
Table 2. Port A Enable Function CSA H L L L L L L L W/RA X H H H L L L L ENA X L H H L H L H MBA X X L H L L H H CLKA X X X X A0-35 Outputs In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO2 output register Active, FIFO2 output register Active, Mail2 register Active, Mail2 register Port Function None None FIFO1 write Mail1 write None FIFO2 read None Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function CSB H L L L L L L L W/RB X L L L H H H H ENB X L H H L H L H MBB X X L H L L H H CLKB X X X X B0-35 Outputs In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO1 output register Active, FIFO1 output register Active, Mail1 register Active, Mail1 register Port Function None None FIFO2 write Mail2 write None FIFO1 read None Mail1 read (set MBF1 HIGH)
Notes: 54. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 55. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
34
PRELIMINARY
Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes) Number of Words in FIFO Memory[56, 57, 58, 59] CY7C43644AV 0 1 TO X1 (X1+1) to [1024-(Y1+1)] CY7C43664AV 0 1 TO X1 (X1+1) to [4096-(Y1+1)] CY7C43684AV 0 1 TO X1 (X1+1) to [16384-(Y1+1)] (16384-Y1) to 16383 16384
CY7C43644AV CY7C43664AV/CY7C43684AV
Synchronized to CLKA EFB/ORB L H H H H AEB L L H H H
Synchronized to CLKB AFA H H H L L FFA/IRA H H H H L
(1024-Y1) to 1023 (4096-Y1) to 4095 1024 4096
Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes) Number of Words in FIFO Memory[57, 58, 60, 61] CY7C43644AV 0 1 TO X2 (X2+1) to [1024-(Y2+1)] (1024-Y2) to 1023 1024 CY7C43664AV 0 1 TO X2 (X2+1) to [4096-(Y2+1)] (4096-Y2) to 4095 4096 CY7C43684AV 0 1 TO X2 (X2+1) to [16384-(Y2+)1] (16384-Y2) to 16383 16384 Synchronized to CLKA EFB/ORB L H H H H AEB L L H H H Synchronized to CLKB AFA H H H L L FFA/IRA H H H H L
Table 6. Data Size for Long-Word Writes to FIFO2 Size Mode[62] BM L SIZE X BE X B27-35 A Data Written to FIFO2 B18-26 B B9-17 C B0-8 D A27-35 A Data Read From FIFO2 A18-26 B A9-17 C A0-8 D
Table 7. Data Size for Word Writes to FIFO2 Size Mode[62] BM H H SIZE L L BE H L 1 2 1 2 Write No. Data Written to FIFO2 B9-17 A C C A B0-8 B D D B A B C D A27-35 A Data Read From FIFO2 A18-26 B A9-17 C A0-8 D
Notes: 56. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming. 57. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 58. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 59. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode. 60. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming. 61. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.quested to the output register (no read operation necessary), it is not included in the FIFO memory count. 62. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
35
PRELIMINARY
Table 8. Data Size for Byte Writes to FIFO2 Size Mode [62] BM H SIZE H BE H 1 2 3 4 H H L 1 2 3 4 Table 9. Data Size for FIFO Long-Word Reads from FIFO1 Size Mode[62] BM L SIZE X BE X A27-35 A Data Written to FIFO1 A18-26 B A9-17 C Write No. Data Written to FIFO2 B0-8 A B C D D C B A
CY7C43644AV CY7C43664AV/CY7C43684AV
Data Read From FIFO2 A27-35 A A18-26 B A9-17 C A0-8 D
A
B
C
D
Data Read From FIFO1 A0-8 D B27-35 A B18-26 B B9-17 C B0-8 D
Table 10. Data Size for Word Reads from FIFO1 Size Mode[62] BM H H SIZE L L BE H L A27-35 A A Data Written to FIFO1 A18-26 B B A9-17 C C A0-8 D D 1 2 1 2 Table 11. Data Size for Byte Reads from FIFO1 Size Mode[62] BM H SIZE H BE H A27-35 A Data Written to FIFO1 A18-26 B A9-17 C A0-8 D 1 2 3 4 H H L A B C D 1 2 3 4 Read No. Data Read From FIFO1 B0-8 A B C D D C B A Read No. Data Read From FIFO1 B9-17 A C C A B0-8 B D D B
36
PRELIMINARY
Ordering Information
3.3V 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed (ns) 7 10 15 Ordering Code CY7C43644AV-7AC CY7C43644AV-10AC CY7C43644AV-15AC Package Name A128 A128 A128
CY7C43644AV CY7C43664AV/CY7C43684AV
Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package
Operating Range Commercial Commercial Commercial
3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed (ns) 7 10 15 Ordering Code CY7C43664AV-7AC CY7C43664AV-10AC CY7C43664AV-15AC Package Name A128 A128 A128 Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package Operating Range Commercial Commercial Commercial
3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Speed (ns) 7 10 15 15 Ordering Code CY7C43684AV-7AC CY7C43684AV-10AC CY7C43684AV-15AC CY7C43684AV-15AI Package Name A128 A128 A128 A128 Package Type 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package 128-Lead Thin Quad Flat Package Operating Range Commercial Commercial Commercial Industrial
Shaded area contains advance information.
Document #: 38-00777
37
PRELIMINARY
Package Diagram
CY7C43644AV CY7C43664AV/CY7C43684AV
128-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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